The present invention relates to bipolar transistor monolithic integrated circuit memories and, more particularly, to such memories providing random access to the memory cells therein at least in part through selecting a row of such cells from among the rows thereof provided in the integrated circuit.
Monolithic integrated circuit structural features have been shrinking rapidly in size in recent years. As a result, greater numbers of circuit components and circuit portions can be provided in monolithic integrated circuit chips of a size approximately the same as used with earlier technology. The resulting increase in circuit density reduces costs, reduces sizes required for electronic systems, and increases the rapidity of operation of the circuits. The cost reduction has been especially marked in metal-oxide-semiconductor field-effect transistor (MOSFET) based monolithic integrated circuits, but it has also been true of bipolar monolithic integrated circuits which continue to maintain some advantage in rapidity of operation over that achieved by MOS circuits.
One of the impediments to rapid rates of switching in bipolar monolithic integrated circuit memory chips providing random access to the memory cells therein is the need to discharge the capacitances associated with the row or word lines (interconnections) used in operating the rows of memory cells therein. This need arises for specific word lines associated with a memory cell row that had been selected by the address decoder circuitry to which such lines are connected, but which selection thereafter ceases.
The selection of the row of memory cells occurs by the address decoder circuitry raising the voltage on the word lines connected to the selected row of memory cells which, in operating that row, also charges the parasitic capacitances associated therewith. Ending such a selection of a row of memory cells requires that the relatively high selection voltage thereon be lowered, and so the parasitic capacitances connected to that word line must be discharged to the standby voltage level. This discharge should occur as rapidly as possible since satisfactory memory operation makes unacceptable having more than one row of memory cells selected simultaneously beyond a transient switching period by having a relatively high voltage in the word lines connected to each. Thus, the selecting of another row is usually not permitted to occur until the selection of the preceding row of memory cells has proceeded significantly toward termination by the voltage on the word lines connected thereto having reached a sufficiently low level.
The needed discharging of word lines after the termination of the selection of the corresponding row of memory cells is usually aided by the provision of a word line discharge circuit in the monolithic integrated circuit bipolar memory containing these cells. In many instances, these circuits have shortcomings such as requiring overly large circuit components, drawing current out of word lines after the selection of the corresponding row of memory cells has ceased, and drawing currents during such a cessation process that decrease during the process slowing its completion. Several other kinds of problems can also exist with such circuits. Thus, there is a desire for a word line discharge circuit overcoming these problems.